Researchers Submit Patent Application, “Semiconductor Structure With Substantially Straight Contact Profile”, for Approval (USPTO 20190229063)

Electronic Business Daily |

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Electronics Business Daily -- From Washington, D.C., NewsRx journalists report that a patent application by the inventors NAUMANN, Ronald (Dresden, DE); ZINKE, Matthias (Dresden, DE); SEIDEL, Robert (Dresden, DE); BARCHEWITZ, Tobias (Radebeul, DE), filed on , was made available online on .

The patent’s assignee is GLOBALFOUNDRIES Inc. (Grand Cayman, Cayman Islands).

News editors obtained the following quote from the background information supplied by the inventors: “Semiconductor devices include many different wiring layers. These wiring layers are formed in interlevel dielectric material and may include wiring structures, interconnect contacts, passive devices and active devices. The interconnect contacts are provided in different wiring layers of the die to connect to the different structures, e.g., different wiring structures, etc.

“In manufacturing the semiconductor devices, an adhesion layer is typically formed at a bottom surface of the interlevel dielectric material, e.g., bulk SiCOH materials, above a wiring structure. The adhesion layer, though, has a different etch rate than the interlevel dielectric material, resulting in a tapered via profile. In other words, as the etch rate is different for the interlevel dielectric material and the adhesion layer, these materials will etch at a different rate resulting in a tapered profile within the adhesion layer. The tapered via profile, in turn, leads to interconnect contacts with tapered profiles. This tapered profile of the interconnect contacts leads to electrical performance issues including void formation in the metal material, e.g., copper, as well as and time-dependent gate oxide breakdown (TDDB).

“The etching of these different materials is also known to be difficult to control as it is not possible to measure the thickness of the adhesion layer, in line. And, different thicknesses of the adhesion layer will generate different tapered via profiles.”

As a supplement to the background information on this patent application, NewsRx correspondents also obtained the inventors’ summary information for this patent application: “In an aspect of the disclosure, a structure comprises: a block material comprising an upper oxidized layer at an interface with an insulating material; and an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material.

“In an aspect of the disclosure, a structure comprises: a wiring layer formed in an insulator material; a block material comprising an upper surface composed of oxidized material; an interlevel dielectric material directly on the upper surface; and a contact extending to the wiring layer, through the block material, oxidized material and the interlevel dielectric material, the contact having a substantially straight profile within the oxidized material.

“In an aspect of the disclosure, a method comprises: forming a blocking material over a wiring structure; oxidizing the blocking material to form an upper oxidized layer; forming an interlevel dielectric material over the oxidized layer; etching a via into the interlevel dielectric material, the oxidized layer and the blocking material to expose the wiring structure, the via having a substantially straight via profile through the oxidized layer; and forming a contact within the via, the contact having a substantially straight profile through the oxidized layer.”

The claims supplied by the inventors are:

“1. A method comprising: forming a blocking material over a wiring structure; oxidizing the blocking material to form an upper oxidized layer; forming an interlevel dielectric material over the oxidized layer; etching a via into the interlevel dielectric material, the oxidized layer and the blocking material to expose the wiring structure, the via having a substantially straight via profile through the oxidized layer; and forming a contact within the via, the contact having a substantially straight profile through the oxidized layer.

“2. The method of claim 1, wherein the interlevel dielectric material and the oxidized layer have a substantially same etch profile.

“3. The method of claim 2, wherein oxidizing is performed in a deposition chamber which is used to form the blocking material.

“4. The method of claim 2, wherein the oxidizing is performed with a plasma process.

“5. The method of claim 1, wherein the blocking material is composed of nitride material.

“6. The method of claim 5, wherein the oxidized layer is at an interface with the interlevel dielectric material is composed of SiCOH.

“7. The method of claim 5, wherein the oxidized layer is about 20% to 30% of a thickness of the blocking material.

“8. The method of claim 5, wherein the blocking material is composed of nitrogen-doped silicon carbide.

“9. The method of claim 1, wherein the blocking material is composed of a low-k dielectric material.

“10. The method of claim 9, wherein a thickness of the blocking material and a thickness of the oxidized layer are balanced such that remaining block material thickness is structured to act as a diffusion barrier.

“11. The method of claim 10, wherein the oxidized layer has a thickness of about 12 nm to 25 nm.

“12. The method of claim 1, wherein the oxidized layer is formed by an oxygen treatment provided in an oxygen atmosphere.

“13. The method of claim 12, wherein the oxygen atmosphere is one of O.sub.2, NO.sub.2 and CO.sub.2, in a carrier gas in a deposition chamber.

“14. The method of claim 13, wherein the oxygen treatment is provided after start of the deposition process using the same deposition chamber as deposition for the blocking material.

“15. The method of claim 14, wherein the oxygen treatment is after the start of the deposition process of the blocking material.

“16. The method of claim 14, wherein the oxygen treatment is an in situ deposition process with the blocking material.”

For additional information on this patent application, see: NAUMANN, Ronald; ZINKE, Matthias; SEIDEL, Robert; BARCHEWITZ, Tobias. Semiconductor Structure With Substantially Straight Contact Profile. Filed and posted . Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190229063%22.PGNR.&OS=DN/20190229063&RS=DN/20190229063

(Our reports deliver fact-based news of research and discoveries from around the world.)

DISCLOSURE: The views and opinions expressed in this article are those of the authors, and do not represent the views of equities.com. Readers should not consider statements made by the author as formal recommendations and should consult their financial advisor before making any investment decisions. To read our full disclosure, please go to: http://www.equities.com/disclaimer.

Comments

Watchlist

Symbol Last Price Change % Change
AAPL

     
AMZN

     
HD

     
JPM

     
IBM

     
BA

     
WMT

     
DIS

     
GOOG

     
XOM

     
BRK.A

     
FB

     
JNJ

     
WFC

     
T

     
NFLX

     
TSLA

     
V

     
UNH

     
PG

     

World Economic Forum at Davos 2019 - Joseph Weinberg CEO PayCase, Chairman Shyft

Matt Bird sits down with Joseph Weinberg CEO PayCase, Chairman Shyft at the World Economic Forum at Davos 2019