Patent Issued for Template-Based Real Number Behavioral Modeling

By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Foster, Paul C. (Scotts Valley, CA); Hartong, Walter E. (Isen, DE); O'Leary, T. Martin (San Jose, CA), filed on January 22, 2010, was cleared and issued on December 4, 2012.

The assignee for this patent, patent number 8327303, is Cadence Design Systems, Inc. (San Jose, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "This disclosure relates in general to electronic design automation (EDA) tool systems and, but not by way of limitation, to real number behavioral modeling.

"Simulation of a circuit design with a digital EDA tool lacks the precision of analog simulation of the circuit design. Analog simulation is time intensive and impractical in many situations. Circuit design typically involves working with both digital and analog simulation in different realms having different tools and verification. There is little coordination between these tools and flaws are often not uncovered until the latter stages of the design process causing costly and time consuming rework.

"To avoid problems in an application specific integrated circuit (ASIC), design verification and testing is a critical part of mixed signal designs. To assure good success, full functional verification is often performed at the transistor level. This type of verification is slow on large designs and not practical. During the design process, different blocks may or may not have a transistor level equivalent making full functional verification difficult to do until near the end of the process."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In one embodiment, the present disclosure provides template-based behavioral model creation to behaviorally model a design. A design characterization and modeling (DCM) tool has a number of templates to different circuits. A designer chooses a template and customizes the template with a number of parameters and possibly pin assignments. The DCM tool generates a behavioral model that has real wire ('Wreal') capability along with possibly other generated models. The transistor level design is simulated with a testbench according to the parameters to generate Wreal calibration information. The behavioral model uses the Wreal calibration information to provide quick behavioral processing of the behavioral model with the benefit of increased accuracy provided by the Wreal calibration information, for example. Optionally, the DCM tool validates that the behavioral models matches the transistor level design using the testbench.

"In another embodiment, the present disclosure provides an electronic design automation (EDA) tool system to process behavioral models of an transistor level design, the EDA tool system comprising a model generation function, an analog EDA tool and a behavioral EDA tool. The model generation function is configured to: receive selection of a template from a plurality of templates, wherein the template corresponds to the transistor level design, receive a plurality of parameters, and generate a first model wherein the first model is configured to take into account analog behavior of the transistor level design. The analog EDA tool configured to generate real number calibration information according to the plurality of parameters. The real number calibration information is indicative of analog operation of the transistor level design. The behavioral EDA tool is configured to: automatically receive the real number calibration information, and simulate the transistor level design as a function of the real number calibration information.

"In yet another embodiment, the present disclosure provides a computer-implemented method to process a transistor level design using templates. Selection of a template from a plurality of templates is received along with a plurality of parameters. A first model is generated that is configured to take into account analog behavior of the transistor level design. Real number calibration information is generated according to the plurality of parameters, where the real number calibration information is indicative of analog operation of the transistor level design. The transistor level design is simulated as a function of the real number calibration information in a behavioral modeling tool.

"In still another embodiment, the present disclosure provides a computer-readable medium with software to execute on a computing system, the computer-readable medium comprising code for: receiving selection of a template from a plurality of templates; receiving a plurality of parameters; generating a first model, wherein the first model is configured to take into account analog behavior of the transistor level design; generating real number calibration information according to the plurality of parameters, wherein the real number calibration information is indicative of analog operation of the transistor level design; and simulating the transistor level design as a function of the real number calibration information in a behavioral modeling tool.

"Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating various embodiments, are intended for purposes of illustration only and are not intended to necessarily limit the scope of the disclosure."

For more information, see this patent: Foster, Paul C.; Hartong, Walter E.; O'Leary, T. Martin. Template-Based Real Number Behavioral Modeling. U.S. Patent Number 8327303, filed January 22, 2010, and issued December 4, 2012. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=12&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=587&f=G&l=50&co1=AND&d=PTXT&s1=20121204.PD.&OS=ISD/20121204&RS=ISD/20121204

Keywords for this news article include: Cadence Design Systems Inc.

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